Fabrication of semiconductor wafers includes, among other process acts, sequential acts of forming a photoresist material to be patterned on a surface of a semiconductor wafer, exposing portions of the photoresist material to electromagnetic radiation to transfer a pattern of a reticle (i.e., a mask) to the photoresist material, and developing the exposed photoresist material to produce the image of the reticle on the wafer. The reticle includes a pattern of radio-opaque and radio-transmissive areas that may define features of the circuit pattern when transferred to the wafer.
Each level of the semiconductor wafer may be aligned to the previously formed and patterned levels. Conventionally, special alignment patterns may be designed on each level of the semiconductor wafer to align the wafer to the reticle or to measure a lateral misregistration between adjacent levels of the wafer. During photolithography processes, the pattern on the reticle is aligned with the pattern on a surface of the wafer underlying the photoresist material to be patterned.
Relatively small errors in the lateral positioning of features of adjacent levels of the semiconductor wafer may result in an ineffective semiconductor device fabricated from the wafer. For example, relatively small errors in positioning of an access line relative to a conductive via can cause the conductive via to be offset from the access line or to contact the line over a surface area that is insufficient to provide adequate conductivity for a fully functional circuit. In addition, relatively small errors may be compounded in the case of stacked, so-called three-dimensional semiconductor devices, such as hybrid memory cubes comprising a stack of memory dice on a logic dice.
Overlay accuracy generally refers to how accurately a first patterned level of a wafer aligns with respect to a second patterned level of the wafer disposed above or below the first patterned level. Misregistration refers to an amount of lateral offset between one or more levels of the wafer and one or more other levels of the wafer. By way of nonlimiting examples, misregistration may refer to a lateral offset between one semiconductor die in a stack of semiconductor dice relative to other semiconductor dice in the stack, or between features on or in different levels of a semiconductor structure, such as a semiconductor wafer or die. Accuracy of the misregistration measurement in terms of magnitude and direction is still one of the major challenges faced by the overlay metrology in advanced integrated circuits.
Previous methods of measuring the misregistration include the so called “box-in-box” method wherein a target including a pair of concentric boxes (i.e., squares) are formed in scribe lines of the wafer. A location of the edges of each box is determined with, for example, an optical microscope waveform or a scanning electron microscope (SEM) waveform. The overlay error is calculated by estimating a location of the edges of each box with the waveform, determining a distance between relative edges of an inner box and an outer box, and calculating each of the horizontal offset and vertical offset. Other examples of overlay targets include the so called “bar-in-bar” target which includes pairs of parallel bars on successive layers of the wafer.
Unfortunately, such conventional methods of measuring lateral misregistration are prone to errors. Errors in the measurement may be introduced by, for example, insufficient imaging of an entire edge of each box, thick photoresist materials, insufficient contrast between patterns on the wafer, or a nonuniform wafer surface topography. In such situations, current methods of measuring a misregistration are not capable of measuring the misregistration with sufficient accuracy. In some cases, the measured misregistration employing such methods is greater than the actual lateral offset in the wafer, giving a manufacturer a false indication that the tested wafer is not within manufacturing tolerances.